Reinforcement learning for chip design
Daniel and Chris have a fascinating discussion with Anna Goldie and Azalia Mirhoseini from Google Brain about the use of reinforcement learning for chip floor planning - or placement - in which many new designs are generated, and then evaluated, to find an optimal component layout. Anna and Azalia also describe the use of graph convolutional neural networks in their approach.
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Good to see the application of RL in chip design. I am from chip design back ground good to see he optimization engine which continuously learn over period of time. In placement stage we optimize all the three costs (area-congestion, power and timing) . Having only weighted wire load based cost how the timing is improved? Since this is not timing aware how it is expected to have better timing w.r.t to traditional placement engines. Also please point me if you have any publication on graph based neural network.